PLEASE NOTE THAT THE SEMINAR STARTS AT 2.30PM

Dear ICTP Community,

We warmly invite you to the (online) MHPC seminar given by Leon Vega Luis
Gerardo (RidgeRun LLC; Costa Rica Institute of Technology) on the topic of
"Energy Efficiency with Cooperative Heterogeneous Computing and
Cutting-Edge Compute Architecture Trends" tomorrow, May 26 at 2.30pm (until
5pm).

Location: The seminar will be broadcasted at MHPC lecture room (old SISSA
building, 1st floor, white door on the stairs from the ICTP tunnel), those
willing to join through zoom please contact Irina at idavyden@ictp.it for
connection details.

Abstract:

The rapid evolution of artificial intelligence workloads, particularly
large language models (LLMs), is exposing fundamental limitations in
current computng architectures in terms of energy efficiency, memory
bandwidth, and long-term adaptability. While GPUs dominate AI training and
inference today, their performance-per-watt and flexibility increasingly
fall short for emerging workloads. This seminar explores architectural
insights for the next generation of AI computers, drawing on recent
advances in cooperative heterogeneous computing, reconfigurable
architectures, and near-data processing.

We examine the comparative strengths and weaknesses of CPUs, GPUs, FPGAs,
ASICs, and Processing-in-Memory (PIM) systems, highlighting how no single
architecture can efficiently address both compute-bound and memory-bound
AI workloads. Cooperative Heterogeneous Computing (CHC) is presented as a
promising paradigm in which multiple specialized architectures
collaborate, with energy-aware workload partitioning and scheduling
playing a central role. The seminar discusses key challenges in CHC,
including workload distribution, memory and I/O communication, and
software complexity, and classifies optimization strategies into
compute-oriented and memory-oriented improvements.

Reconfigurable computing emerges as a critical enabler for future AI
systems. Fine- and coarse-grained reconfigurable architectures—such as
FPGAs, CGRAs, and reconfigurable RISC-V-based accelerators—offer
adaptability to evolving numerical formats, approximate computing
techniques, and sparsity patterns, reducing hardware obsolescence.
Additionally, reconfigurable PIM/Near-Data Processing architectures are
explored as an effective solution for accelerating
low-arithmetic-intensity operations by bringing computation closer to
memory.

The seminar concludes by outlining a unified, energy-driven architectural
roadmap in which reconfigurability is deployed across execution units,
accelerators, and memory systems. Such architectures promise improved
performance-per-watt, fine-grained control over numerical precision, and
sustained relevance in the face of rapidly evolving AI models, positioning
reconfigurable CHC systems as a cornerstone of next-generation AI
computing platforms.

Best regards,
Irina Davydenkova,
MHPC program coordinator